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IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
(3D-TEST)
November 17+18, 2016
Convention Center – Fort Worth, TX, USA (in conjunction with ITC / Test Week 2016)

http://3dtest.tttc-events.org

CALL FOR PAPERS

Scope

The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs), micro-bumps, and/or interposers. While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.

3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of IEEE Computer Society.

Topic Areas – You are invited to participate and submit your contributions to the 3D-TEST Workshop. The workshop’s areas of interest include (but are not limited to) the following topics:

  • Defects due to Wafer Thinning
  • Defects in Intra-Stack Interconnects
  • DfT Architectures for 3D-SICs
  • EDA Design-to-Test Flow for 3D-SICs
  • Failure Analysis for 3D-SICs
  • Fault-Tolerant Design for 3D-SICs
  • Handling and Testing Singulated Stacks
  • Interposer Testing
  • Known-Good Die / Stack Testing
  • Power and Heat Dissipation during Test
  • Pre-Bond, Mid-Bond and Post-Bond Test
  • Reliability of 3D-SICs
  • Stacking Yield of Dies and Interconnects
  • Standardization for 3D Testing
  • Supply Chain and Logistic Issues
  • System/Board Test Issues for 3D-SICs
  • Test Cost Modeling for 3D-SICs
  • Test Flow Optimization for 3D-SICs
  • Tester Architecture incl. ATE and BIST
  • Thermal/Mechanical Stress in 3D-SICs
  • TSV Test, Redundancy, and Repair
  • Wafer Probing and Probe Marks of 3D-SICs

Submissions

Submission Instructions – Submissions must be sent in PDF. The Workshop prefers Full Paper submissions (of up to six pages), but also allows Extended Abstract submissions (of at least two pages). Detailed submission instructions can be found at the Workshop’s website: http://3dtest.tttc-events.org. All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, technical soundness, and presented results. Selected submissions can be accepted for regular or poster presentation at the Workshop.

Publications – The workshop will make available to all participants an Electronic Workshop Digest, which includes all material that authors are willing to provide in PDF: abstract, paper, slides, poster, background material, etc. 

Key Dates

  • Submission deadline: October 1, 2016 (23:59h PDT)
  • Notification of acceptance: October 15, 2016
  • Camera-ready material: November 1, 2016 (23:59h PDT)
Additional Information

General Chair:

Yervant Zorian
Synopsys
700 East Middlefield Road
Mountain View, CA, USA
Tel.: +1 (650) 584-7120
yervant.zorian@synopsys.com

Program Chair:

Erik Jan Marinissen
IMEC
Kapeldreef 75
B-3001 Leuven, Belgium
Tel.: +32 16 28-8755
erik.jan.marinissen@imec.be

Program Vice-Chair:

Shi-Yu Huang
National Tsing-Hua University
101, Sec. 2, Kuang-Fu Road HsinChu, Taiwan
Tel.: +886 3-573-1147
syhuang@ee.nthu.edu.tw

Committee

General Chair:
Y. Zorian – Synopsys (US)

Program Chair / Vice Chair:
E.J. Marinissen – IMEC (BE)
S.-Y. Huang – NTHU (TW)

Finance Chair:
C.-H. Chiang – Intel (US)

Panel Chair:
E.J. Vardaman – TechSearch (US)

Publication Chair:
M. Chern – NTHU (TW)

Publicity Chair:
F. von Trapp – 3DInCites (US)

Web Chair:
G. Jervan – TU Tallinn (EE)

Arrangements Chair:
J. Potter – (US)

Program Committee Members:
S. Adham  – TSMC (CAN)
V. Agrawal – Auburn Univ. (US)
D. Armstrong – Advantest (US)
S. Bhatia – Google (US)
K. Chakrabarty – Duke Univ. (US)
K.Y. Chung – Qualcomm (US)
E. Cormack – DfT Solutions (UK)
A. Cron – Synopsys (US)
A. Crouch – (US)
M.-L. Flottes – LIRMM (FR)
P. Franzon – NC State Univ. (US)
S.K. Goel – TSMC (US)
M. Hutner – Teradyne (CAN)
L. Jiang – SJTU (CN)
H. Jiao – TU Eindhoven (NL)
H. Jun – SK hynix (KR)
S. Kameyama – Fujitsu (JP)
S. Lecomte – Intel (DE)
C.M. Li – NTU (TW)
M. Loranger – FormFactor (US)
A. Majumdar – Xilinx (US)
T. McLaurin – ARM (US)
B. Nadeau-Dostie – Mentor (CAN)
B. Noia – AMD (US)
C. Papameletis – Cadence (US)
R. Parekhji – Texas Instruments (IN)
M. Ricchetti – Synopsys (US)
S. Shaikh – Broadcom (US)
K. Smith – Cascade Microtech (US)
R. Vallauri – Technoprobe (IT)
P. Vivet – CEA-Leti (FR)
M. Wahl – Univ. Siegen (DE)

For more information, visit us on the web at: http://3dtest.tttc-events.org

The CONFERENCE is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

PAST CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

TTTC 1ST VICE CHAIR
Chen-Huan CHIANG
Alcatel-Lucent - USA
E-mail chen-huan.chiang@alcatel-lucent.com

SECRETARY
Joan FIGUERAS
Un. Politec. de Catalunya - Spain
Tel. +34-93-401-6603
E-mail figueras@eel.upc.es

ITC GENERAL CHAIR
Michael Purtell
Intersil
- USA
Tel. +1-408-372-6015
E-mail m.purtell@ieee.org

TEST WEEK COORDINATOR
Yervant ZORIAN
Synopsys, Inc. - USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

TUTORIALS AND EDUCATION
Paolo BERNARDI

Politecnico di Torino
- Italy
Tel. +39-011-564-7183
E-mail paolo.bernardi@polito.it

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Giorgio DI NATALE
LIRMM - France
Tel. +33-467-41-85-01
E-mail giorgio.dinatale@lirmm.fr

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Giorgio DI NATALE
LIRMM - France
Tel. +33-467-41-85-01
E-mail giorgio.dinatale@lirmm.fr

 

PRESIDENT OF BOARD
Yervant ZORIAN
Synopsys, Inc. - USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

SENIOR PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 2ND VICE CHAIR
Rohit KAPUR

Synopsys, Inc.
- USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

FINANCE
Chen-Huan CHIANG
Alcatel-Lucent - USA
E-mail chen-huan.chiang@alcatel-lucent.com

IEEE DESIGN & TEST EIC
André IVANOV
U. of British Columbia - Canada
Tel. +1
E-mail ivanov@ece.ubc.ca

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39 090 7055
E-mail patrick.girard@lirmm.fr

ASIA & PACIFIC
Kazumi HATAYAMA
NAIST - Japan
Tel.+81-743-72-5221
E-mail k-hatayama@is.naist.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Synopsys, Inc. - USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com


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